Jingning Liu
Orcid: 0000-0002-2680-7422
According to our database1,
Jingning Liu
authored at least 79 papers
between 2007 and 2024.
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Bibliography
2024
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage.
IEEE Trans. Computers, 2021
J. Syst. Archit., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Access, 2020
MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
CCHL: Compression-Consolidation Hardware Logging for Efficient Failure-Atomic Persistent Memory Updates.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
IEEE Trans. Computers, 2019
Exploiting flash memory characteristics to improve performance of RAIS storage systems.
Frontiers Comput. Sci., 2019
Proceedings of the 2019 IEEE International Conference on Networking, 2019
CeSR: A Cell State Remapping Strategy to Reduce Raw Bit Error Rate of MLC NAND Flash.
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
CACF: A Novel Circuit Architecture Co-optimization Framework for Improving Performance, Reliability and Energy of ReRAM-based Main Memory System.
ACM Trans. Archit. Code Optim., 2018
Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive Memory Architecture.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
A High-Performance and High-Reliability RAIS5 Storage Architecture with Adaptive Stripe.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018
An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
ACM Trans. Storage, 2017
IEEE Trans. Computers, 2017
一种基于热数据识别技术的UBIFS优化方案 (Optimization Scheme of UBIFS Based on Hot Data Identification Technology).
计算机科学, 2017
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Reducing Fragmentation for In-line Deduplication Backup Storage via Exploiting Backup History and Cache Knowledge.
IEEE Trans. Parallel Distributed Syst., 2016
ACM Trans. Archit. Code Optim., 2016
A user-visible solid-state storage system with software-defined fusion methods for PCM and NAND flash.
J. Syst. Archit., 2016
Prober: exploiting sequential characteristics in buffer for improving SSDs write performance.
Frontiers Comput. Sci., 2016
A Stripe-Oriented Write Performance Optimization for RAID-Structured Storage Systems.
Proceedings of the IEEE International Conference on Networking, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 45th International Conference on Parallel Processing, 2016
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016
Application-Aware and Software-Defined SSD Scheme for Tencent Large-Scale Storage System.
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Int. J. Comput. Sci. Eng., 2015
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the 10th IEEE International Conference on Networking, 2015
Fast FCoE: An Efficient and Scale-Up Multi-core Framework for FCoE-Based SAN Storage Systems.
Proceedings of the 44th International Conference on Parallel Processing, 2015
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015
2014
Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks.
ACM Trans. Archit. Code Optim., 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the International Conference on Cloud Computing and Big Data, 2014
2013
Proceedings of the Grid and Pervasive Computing - 8th International Conference, 2013
2012
Math. Comput. Model., 2012
Proceedings of the Seventh IEEE International Conference on Networking, 2012
Proceedings of the 26th International Conference on Advanced Information Networking and Applications Workshops, 2012
2010
Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation.
Proceedings of the IEEE 26th Symposium on Mass Storage Systems and Technologies, 2010
Proceedings of the Third International Symposium on Intelligent Information Technology and Security Informatics, 2010
TRIP: Temporal Redundancy Integrated Performance Booster for Parity-Based RAID Storage Systems.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010
Design and Implementation of Object-Oriented Encryption Storage System Based on Trusted Computing Platform.
Proceedings of the 2010 International Conference on Computational Intelligence and Security, 2010
2009
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009
2008
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008
TSPSCDP: A Time-Stamp Continuous Data Protection Approach Based on Pipeline Strategy.
Proceedings of the Japan-China Joint Workshop on Frontier of Computer Science and Technology, 2008
2007
Proceedings of the Future Generation Communication and Networking, 2007
SDBIA: A Novel Approach to Improve the Reading Performance of Large Objects for Object-Based Storage Device.
Proceedings of the Japan-China Joint Workshop on Frontier of Computer Science and Technology, 2007