Jinghong Chen

Orcid: 0000-0001-8650-790X

According to our database1, Jinghong Chen authored at least 70 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
On Extending Direct Preference Optimization to Accommodate Ties.
CoRR, 2024

Few-Shot VQA with Frozen LLMs: A Tale of Two Approaches.
CoRR, 2024

Direct Preference Optimization for Neural Machine Translation with Minimum Bayes Risk Decoding.
Proceedings of the 2024 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies: Short Papers, 2024

Control-DAG: Constrained Decoding for Non-Autoregressive Directed Acyclic T5 using Weighted Finite State Automata.
Proceedings of the 2024 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies: Short Papers, 2024

Improving Hateful Meme Detection through Retrieval-Guided Contrastive Learning.
Proceedings of the 62nd Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2024

PreFLMR: Scaling Up Fine-Grained Late-Interaction Multi-modal Retrievers.
Proceedings of the 62nd Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2024

2023
A Real-Time Respiration Monitoring System Using WiFi Sensing Based on the Concentric Circle Model.
IEEE Trans. Biomed. Circuits Syst., April, 2023

Self-Supervised 3D Behavior Representation Learning Based on Homotopic Hyperbolic Embedding.
IEEE Trans. Image Process., 2023

HMANet: Hyperbolic Manifold Aware Network for Skeleton-Based Action Recognition.
IEEE Trans. Cogn. Dev. Syst., 2023

STAGER checklist: Standardized Testing and Assessment Guidelines for Evaluating Generative AI Reliability.
CoRR, 2023

Improving hateful memes detection via learning hatefulness-aware embedding space through retrieval-guided contrastive learning.
CoRR, 2023

Schema-Guided Semantic Accuracy: Faithfulness in Task-Oriented Dialogue Response Generation.
CoRR, 2023

Grounding Description-Driven Dialogue State Trackers with Knowledge-Seeking Turns.
Proceedings of the 24th Meeting of the Special Interest Group on Discourse and Dialogue, 2023

Fine-grained Late-interaction Multi-modal Retrieval for Retrieval Augmented Visual Question Answering.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A 88%-Peak-Efficiency 10-mV-Voltage-Ripple Dual-Mode Switched-Capacitor DC-DC Converter for Ultra-Low-Power Battery Management.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A High-Gain and Low-Noise Mixer with Hybrid $G_{m}$-Boosting for 5G FR2 Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A 24 GHz FMCW/Doppler Dual-Mode Frequency Synthesizer With 68.8 kHz RMS FM Error and 1.25 GHz Chirp Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Real-time Respiration Monitoring System Using WiFi-Based Radar Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 23.4-27.6 GHz "Zig-Zag" VCO with Continuous Frequency Switching for FMCW Radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 71-86 GHz Cascaded Harmonic Enhanced Tripler with -69 dBc Fundamental and -66 dBc Second Harmonic Suppression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers.
Sensors, 2021

A 64-84 GHz CMOS LNA with Excellent Gain Flatness for Wideband mmW Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 22-33 GHz Wideband CMOS LNA Using Low-k Non-inverting MCCRs for 5G mmW Communication Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Toward Customized Hybrid Fuel-Cell and Battery-powered Mobile Device for Individual Users.
ACM Trans. Embed. Comput. Syst., 2020

A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration.
IEEE J. Solid State Circuits, 2020

Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A Bandwidth-Tracking Self-Biased 5-to-2800 MHz Low-Jitter Clock Generator in 55nm CMOS.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A Current Reuse Wideband LNA with Complementary Noise and Distortion Cancellation for Ultrasound Imaging Applications.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

RFI mitigating receiver back-end for radiometers.
Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017

2016
Wireless Networking Testbed and Emulator (WiNeTestEr).
Comput. Commun., 2016

Wideband LNA with 1.9 dB noise figure in 0.18 µm CMOS for high frequency ultrasound imaging applications.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
Effect of OPAMP Input Offset on Continuous-Time ΔΣ Modulators With Current-Mode DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Wideband LNA and multi-standard frequency synthesizer for reconfigurable radio.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Wireless networking testbed and emulator (WiNeTestEr).
Proceedings of the 17th ACM International Conference on Modeling, 2014

2013
A Subthreshold-MOSFETs-Based Scattered Relative Temperature Sensor Front-End With a Non-Calibrated ±2.5°C 3σ Relative Inaccuracy From -40°C to 100°C.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A radiation-hardened DLL with fine resolution and DCC for DDR2 memory interface in 0.13 μm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Efficient Measurement of Impulses Based on Frequency-Domain Approach.
IEEE Trans. Instrum. Meas., 2012

A 30mW 10b 250MS/s dual channel SHA-less pipeline ADC in 0.18µm CMOS.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A radiation-tolerant ring oscillator phase-locked loop in 0.13µm CMOS.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 12b 60MS/s SHA-less opamp-sharing pipeline A/D with switch-embedded dual input OTAs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An all-CMOS low supply voltage temperature sensor front-end with error correction techniques.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A PVT-robust current-mode passive mixer with source-degenerated transconductance amplifier.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A time-to-digital converter based AFC for wideband frequency synthesizer.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver.
IEEE J. Solid State Circuits, 2011

2010
Infrequent Purchased Product Recommendation Making Based on User Behaviour and Opinions in E-commerce Sites.
Proceedings of the ICDMW 2010, 2010

2008
A circuit-compatible analytical device model for ballistic nanowire transistors.
Microelectron. J., 2008

2006
A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication.
IEEE J. Solid State Circuits, 2006

2005
An integrated CMOS transceiver for a 40Gb/s SCM optical communication system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2001
Modeling and Simulation of Integrated Microstructures and Systems
PhD thesis, 2001

Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
An algorithm for automatic model-order reduction of nonlinear MEMS devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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