Jingcheng Zhuang

According to our database, Jingcheng Zhuang authored at least 16 papers between 2003 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

Design of Spur-Free ΣΔ Frequency Tuning Interface for Digitally Controlled Oscillators.

Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction.

Jingcheng Zhuang, Robert Bogdan Staszewski

IPSJ Trans. Syst. LSI Des. Methodol., 2014

2013

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL.

Jingcheng Zhuang, Robert Bogdan Staszewski

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

A low-power all-digital PLL architecture based on phase prediction.

Jingcheng Zhuang, Robert Bogdan Staszewski

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End.

Jingcheng Zhuang, Bruce Andrew Doyle, Emerson S. Fang

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers.

Jingcheng Zhuang

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010

A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter.

Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

IEEE Trans. Very Large Scale Integr. Syst., 2009

2007

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An eye detection technique for clock and data recovery applications.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005

A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the Third IASTED International Conference on Circuits, 2005

2003

A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer.

Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003