Jingang Wu

According to our database1, Jingang Wu authored at least 9 papers between 2006 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A self-adaptive write driver with fast termination of step-up pulse for ReRAM.
IEICE Electron. Express, 2016

2015
A low cost and high reliability true random number generator based on resistive random access memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
IEEE J. Solid State Circuits, 2013

Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Variation-tolerant Cu<sub>x</sub>Si<sub>y</sub>O-based RRAM for low power application.
IEICE Electron. Express, 2012

2006
Stability analysis of a ratio-dependent predator-prey system with diffusion and stage structure.
Int. J. Math. Math. Sci., 2006


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