Jing Ye
Orcid: 0000-0002-8023-5090Affiliations:
- Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Processors/State Key Laboratory of Computer Architecture, Beijing, China
According to our database1,
Jing Ye
authored at least 73 papers
between 2008 and 2025.
Collaborative distances:
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Bibliography
2025
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow.
Integr., 2025
2024
IEEE Trans. Inf. Forensics Secur., 2024
Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262.
Proceedings of the IEEE International Test Conference in Asia, 2024
Proceedings of the IEEE International Test Conference in Asia, 2024
A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256.
Proceedings of the IEEE European Test Symposium, 2024
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning.
J. Supercomput., 2023
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Entropy Sources Based on Silicon Chips: True Random Number Generator and Physical Unclonable Function.
Entropy, 2022
Proceedings of the Uncertainty in Artificial Intelligence, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Reliability Evaluation of Approximate Arithmetic Circuits Based on Signal Probability.
Proceedings of the IEEE International Test Conference in Asia, 2021
ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption.
Proceedings of the 30th IEEE Asian Test Symposium, 2021
2020
INOR - An Intelligent noise reduction method to defend against adversarial audio examples.
Neurocomputing, 2020
MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection.
IEEE Access, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
Integr., 2019
Proceedings of the IEEE International Test Conference in Asia, 2019
Proceedings of the IEEE International Test Conference in Asia, 2019
iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Robotics Autom. Lett., 2018
Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach.
Sci. China Inf. Sci., 2018
Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 2018 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
IEICE Trans. Inf. Syst., 2017
GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image.
Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017
VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
2013
Proceedings of the Design, Automation and Test in Europe, 2013
2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the Design, Automation and Test in Europe, 2010
Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.
Proceedings of the 17th IEEE Asian Test Symposium, 2008