Jing-Yang Jou
According to our database1,
Jing-Yang Jou
authored at least 127 papers
between 1986 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2005, "For contributions to the computer aided design of digital circuits.".
Timeline
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On csauthors.net:
Bibliography
2024
Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
TNSS: Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024
2023
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Chain-based pin count minimization for general-purpose digital microfluidic biochips.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors.
ACM Trans. Embed. Comput. Syst., 2015
IEEE Trans. Computers, 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
2014
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2014
ACM Trans. Design Autom. Electr. Syst., 2014
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog.
ACM Trans. Design Autom. Electr. Syst., 2014
J. Inf. Sci. Eng., 2014
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Equivalence checking of scheduling with speculative code transformations in high-level synthesis.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
J. Inf. Sci. Eng., 2010
Expandable MDC-based FFT architecture and its generator for high-performance applications.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2009
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Computers, 2007
J. Inf. Sci. Eng., 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
ACM Trans. Design Autom. Electr. Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
IEEE Trans. Computers, 2006
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
FSM-based transaction-level functional coverage for interface compliance verification.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Des. Test Comput., 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
RLC effects on worst-case switching pattern for on-chip buses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An efficient approach for hierarchical submodule extraction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An efficient logic extraction algorithm using partitioning and circuit encoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEEE Des. Test Comput., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
J. Circuits Syst. Comput., 2002
A Practical Approach to Cycle Bound Estimation for Property Checking.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Grouped input power sensitive transition an input sequence compaction technique for power estimation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of ASP-DAC 2001, 2001
2000
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2000
On computing the minimum feedback vertex set of a directed graph bycontraction operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Des. Test Comput., 2000
Proceedings of the 2000 International Symposium on Physical Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of ASP-DAC 2000, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
ACM Trans. Design Autom. Electr. Syst., 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD.
Proceedings of the IEEE International Conference On Computer Design, 1999
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
A power modeling and characterization method for macrocells using structure information.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
1995
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
1988
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
Proceedings of the International Conference on Parallel Processing, 1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988
1986
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures.
Proc. IEEE, 1986