Jing Tian

According to our database, Jing Tian authored at least 39 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA.

Jing Tian, Bo Wu, Lang Feng, Haochen Zhang, Zhongfeng Wang

IACR Cryptol. ePrint Arch., 2024

2023

Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation.

Lun Ou, Danyang Zhu, Jing Tian, Zhongfeng Wang

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Low-latency Hardware Architecture for VDF Evaluation in Class Groups.

Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang

IEEE Trans. Computers, June, 2023

AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography.

Xiao Hu, Jing Tian, Minghao Li, Zhongfeng Wang

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature.

Yifeng Song, Xiao Hu, Jing Tian, Zhongfeng Wang

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation.

Danyang Zhu, Rongrong Zhang, Lun Ou, Jing Tian, Zhongfeng Wang

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber.

Minghao Li, Jing Tian, Xiao Hu, Zhongfeng Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

An Efficient Hardware Design for Fast Implementation of HQC.

Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Efficient Decryption Architecture for Classic McEliece.

Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

High-Throughput Hardware Implementation for Haraka in SPHINCS+.

Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications.

Huiyang Xiong, Bohang Xiong, Wenhao Wang, Jing Tian, Hao Zhu, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Efficient Homomorphic Convolution Designs on FPGA for Secure Inference.

Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang

IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation.

Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl

IEEE Trans. Computers, 2022

Reduction-Free Multiplication for Finite Fields and Polynomial Rings.

Samira Carolina Oliva Madrigal, Gökay Saldamli, Chen Li, Yue Geng, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç

Proceedings of the Arithmetic of Finite Fields - 9th International Workshop, 2022

An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking.

Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A High-Speed Codec Architecture for Lagrange Coded Computing.

Bohang Xiong, Jing Tian, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber.

Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography.

Jing Tian, Jun Lin, Zhongfeng Wang

IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier.

Jing Tian, Bo Wu, Zhongfeng Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes.

Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang

IEEE Commun. Lett., 2021

A High-Speed Architecture for the Reduction in VDF Based on a Class Group.

Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang

IACR Cryptol. ePrint Arch., 2021

Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers.

Danyang Zhu, Jing Tian, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol.

Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography.

Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes.

Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes.

Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Faster Software Implementation of the SIKE Protocol Based on A New Data Representation.

Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl

IACR Cryptol. ePrint Arch., 2020

Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography.

Jing Tian, Jun Lin, Zhongfeng Wang

IACR Cryptol. ePrint Arch., 2020

A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography.

Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group.

Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference.

Xiao Hu, Jing Tian, Zhongfeng Wang

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders.

Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang

IEEE Commun. Lett., 2019

High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography.

Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li

IACR Cryptol. ePrint Arch., 2019

Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes.

Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang

IEEE Access, 2019

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes.

Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes.

Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications.

Jing Tian, Jun Lin, Zhongfeng Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories.

Jing Tian, Jun Lin, Zhongfeng Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding.

Jing Tian, Jun Lin, Zhongfeng Wang

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018