Jing Jin

Orcid: 0000-0003-3584-5559

Affiliations:
  • Shanghai Jiao Tong University, School of Microelectronics, China


According to our database1, Jing Jin authored at least 68 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core.
IEEE J. Solid State Circuits, February, 2024

Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS.
Microelectron. J., September, 2023

A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization.
IEEE J. Solid State Circuits, September, 2023

A Compact 0.2-1.6 GHz 20 MHz-Bandwidth Passive-LNA Exploiting an N-Path 1:3 Transformer.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.
IEEE J. Solid State Circuits, February, 2023

A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Predictive LSB-First Successive Approximation for SAR Analog-to-Digital Converters.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fast locking Sampling PLL Using Phase Error Eliminator.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 24/48 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with 3-tap FFE in 28 nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., November, 2022

A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 0.023-12 GHz ultra-wideband frequency synthesizer with FOM<sub><i>T</i></sub> of -251.8 dB.
Microelectron. J., 2022

A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique.
Circuits Syst. Signal Process., 2022

A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS.
Microelectron. J., 2021

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction.
Microelectron. J., 2021

An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications.
Microelectron. J., 2021

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS.
Circuits Syst. Signal Process., 2021

A Linearization Technique for Ring VCO Exploiting Bulk-Modulation.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Center Frequency Calibration Technique for Ring VCO Exploiting Delay<sup>-1</sup> Detection.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Enhanced SSCP for Frequency Drift Suppressing in SSPLL.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance.
IEEE Trans. Circuits Syst., 2020

A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling.
IEEE Trans. Circuits Syst., 2020

An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration.
IEEE Trans. Circuits Syst., 2020

A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.
ACM Trans. Design Autom. Electr. Syst., 2019

A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Optimized Modeling Method for Transformer Design.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 0.0558-mm<sup>2</sup> 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOS.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A High-Linear Digital-to-Phase Converter in 40nm CMOS.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A low-cost digital-domain foreground calibration for high resolution SAR ADCs.
Microelectron. J., 2018

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration.
IET Circuits Devices Syst., 2018

A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A wideband simplified transformer-based VCO with digital amplitude calibration.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A passive mixer-first receiver with negative feedback for impedance matching.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A high-speed low-power charge pump with dynamic current matching.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Analysis of Input LCR Matched N-Path Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Wideband dual-mode complementary metal-oxide-semiconductor receiver.
IET Circuits Devices Syst., 2016

2015
A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012
Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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