Jing Jane Li

ACM Trans. Reconfigurable Technol. Syst., September, 2024

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits.

[BibT_eX]

[DOI]

CoRR, 2024

2023

Introduction to the Special Section on FCCM 2022.

[BibT_eX]

[DOI]

Martin C. Herbordt

ACM Trans. Reconfigurable Technol. Syst., December, 2023

DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS.

[BibT_eX]

[DOI]

Linus Y. Wong

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022

Revisiting PathFinder Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Augmenting HLS with Zero-Overhead Application-Specific Address Mapping for Optane DCPMM.

[BibT_eX]

[DOI]

Nicholas Beckwith

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

Software-defined address mapping: a case on 3D memory.

[BibT_eX]

[DOI]

Michael M. Swift

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAs.

[BibT_eX]

[DOI]

Nicholas Beckwith

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM.

[BibT_eX]

[DOI]

Etienne Nowak

IEEE J. Solid State Circuits, 2020

Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Virtualizing FPGAs in the Cloud.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

TOCO: A Framework for Compressing Neural Network Models Based on Tolerance Analysis.

[BibT_eX]

[DOI]

CoRR, 2019

Interleaved Composite Quantization for High-Dimensional Similarity Search.

[BibT_eX]

[DOI]

Stephen J. Wright

Dimitris S. Papailiopoulos

CoRR, 2019

SysML: The New Frontier of Machine Learning Systems.

[BibT_eX]

[DOI]

Alexandros G. Dimakis

Anastasios Kyrillidis

Shivaram Venkataraman

CoRR, 2019

Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications.

[BibT_eX]

[DOI]

Etienne Nowak

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Specialization: A New Path Towards Low Power.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Evaluating Row Buffer Locality in Future Non-Volatile Main Memories.

[BibT_eX]

[DOI]

Justin Meza

Onur Mutlu

CoRR, 2018

CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

An Alternative Analytical Approach to Associative Processing.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Adaptive Quantization of Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Learning Representations, 2018

Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Efficient Large-Scale Approximate Nearest Neighbor Search on OpenCL FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018

Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Challenges and Opportunities: From Near-memory Computing to In-memory Computing.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

RRAM-based reconfigurable in-memory computing architecture with hybrid routing.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Accelerating Large-Scale Graph Analytics with FPGA and HMC.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

Reconfigurable in-memory computing with resistive memory crossbar.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Enabling phase-change memory for data-centric computing: Technology, circuitand system.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

1 Mb 0.41 µm<sup>2</sup> 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

2012

A case for small row buffers in non-volatile main memories.

[BibT_eX]

[DOI]

Justin Meza

Onur Mutlu

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

Phase change memory.

[BibT_eX]

[DOI]

Chung Lam

Sci. China Inf. Sci., 2011

Post-silicon calibration of analog CMOS using phase-change memory cells.

[BibT_eX]

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.

[BibT_eX]

[DOI]

Kunhyuk Kang

Kaushik Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2008

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs.

[BibT_eX]

[DOI]