Jing Huang

Affiliations:
  • SUN Microsystems, Santa Clara, CA, USA
  • Northeastern University, Boston, MA, USA (former)


According to our database1, Jing Huang authored at least 27 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2009
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates.
J. Electron. Test., 2009

2008
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels.
IEEE Trans. Ind. Informatics, 2008

A model for computing and energy dissipation of molecular QCA devices and circuits.
ACM J. Emerg. Technol. Comput. Syst., 2008

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.
J. Electron. Test., 2008

2007
Design of sequential circuits by quantum-dot cellular automata.
Microelectron. J., 2007

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata.
Integr., 2007

On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire.
J. Electron. Test., 2007

An Overview of Nanoscale Devices and Circuits.
IEEE Des. Test Comput., 2007

Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Modeling facet roughening errors in self-assembly by snake tile sets.
Proceedings of the 2007 IEEE International Test Conference, 2007

Testing Reversible One-Dimensional QCA Arrays for Multiple Faults.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Testing Reversible 1D Arrays for Molecular QCA.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Defect tolerance of QCA tiles.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Tile-based QCA design using majority-like logic primitives.
ACM J. Emerg. Technol. Comput. Syst., 2005

A probabilistic analysis of fault tolerance for switch block array in FPGAs.
Int. J. Embed. Syst., 2005

Defect Characterization and Tolerance of QCA Sequential Devices and Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Modeling and Analysis of Jitter in ATE Using Matlab.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Defects and Faults in Quantum Cellular Automata at Nano Scale.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Routability and Fault Tolerance of FPGA Interconnect Architectures.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Quantum Cellular Automata: New Defects and Faults for New Devices.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Design and characterization of an and-or-inverter (AOI) gate for QCA implementation.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Defect Characterization for Scaling of QCA Devices.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Fault Tolerance of Programmable Switch Blocks.
Proceedings of the 2004 Design, 2004


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