Jing-Hong Conan Zhan
According to our database1,
Jing-Hong Conan Zhan
authored at least 22 papers
between 2003 and 2020.
Collaborative distances:
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Bibliography
2020
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2014
28.2 A 0.29mm<sup>2</sup> frequency synthesizer in 40nm CMOS with 0.19psrms jitter and.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications.
IEEE J. Solid State Circuits, 2011
IEEE Commun. Mag., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications.
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
2008
IEEE J. Solid State Circuits, 2008
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-f<sub>T</sub> SiGe process.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003