Jinfeng Kang

Orcid: 0000-0002-6286-0423

According to our database1, Jinfeng Kang authored at least 37 papers between 2009 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
A 3.3-Mbit/s true random number generator based on resistive random access memory.
Sci. China Inf. Sci., November, 2023

An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash.
Sci. China Inf. Sci., April, 2023

Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy.
Sci. China Inf. Sci., February, 2023

A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Floating Gate Transistor-Based Accurate Digital In-Memory Computing for Deep Neural Networks.
Adv. Intell. Syst., December, 2022

Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro for Deep Neural Network Based on Nonvolatile Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A physics-based electromigration reliability model for interconnects lifetime prediction.
Sci. China Inf. Sci., 2021

Flash Memory Array for Efficient Implementation of Deep Neural Networks.
Adv. Intell. Syst., 2021

Novel Weight Mapping Method for Reliable NVM based Neural Network.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
The synthesis method of logic circuits based on the iMemComp gates.
Integr., 2020

2019
A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning.
Sci. China Inf. Sci., 2019

Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing.
Sci. China Inf. Sci., 2019

Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Flash-based Computing in-Memory Scheme for IOT.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Testing of 1T<i>n</i>R RRAM array with sneak path technique.
Sci. China Inf. Sci., 2017

2016
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays.
CoRR, 2016

Physical understanding and optimization of resistive switching characteristics in oxide-RRAM.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Doping profile modification approach of the optimization of HfO x based resistive switching device by inserting AlO x layer.
Sci. China Inf. Sci., 2015

RRAM based synaptic devices for neuromorphic visual systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Modeling and design optimization of ReRAM.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Design guidelines for 3D RRAM cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Parameters extraction on HfOX based RRAM.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2012
Nanoscale observations of resistive switching high and low conductivity states on TiN/HfO<sub>2</sub>/Pt structures.
Microelectron. Reliab., 2012

2010
A novel voltage-type sense amplifier for low-power nonvolatile memories.
Sci. China Inf. Sci., 2010

2009
Challenges of 22 nm and beyond CMOS technology.
Sci. China Ser. F Inf. Sci., 2009


  Loading...