Jindrich Zejda

According to our database, Jindrich Zejda authored at least 7 papers between 1994 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Fundamentals of timing information for test: How simple can we get?

Rohit Kapur, Jindrich Zejda, Thomas W. Williams

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks.

Jindrich Zejda, Li Ding

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

Noise Library Characterization for Large Capacity Static Noise Analysis Tools.

Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

Analytical modeling of crosstalk noise waveforms using Weibull function.

Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2002

General framework for removal of clock network pessimism.

Jindrich Zejda, Paul Frain

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

1996

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution.

Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin

Proceedings of the 1996 European Design and Test Conference, 1996

1994

Gate-level timing verification using waveform narrowing.

Jindrich Zejda, Eduard Cerny

Proceedings of the Proceedings EURO-DAC'94, 1994