Jindo Byun
According to our database1,
Jindo Byun
authored at least 6 papers
between 2011 and 2022.
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Bibliography
2022
A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.
Proceedings of the 47th ESSCIRC 2021, 2021
A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2011
Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques.
IEEE Trans. Instrum. Meas., 2011