Jincheng Yang

Orcid: 0000-0002-3581-9425

According to our database1, Jincheng Yang authored at least 17 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Optimal Robust Policy for Feature-Based Newsvendor.
Manag. Sci., 2024

Coarse-Fine Spectral-Aware Deformable Convolution For Hyperspectral Image Reconstruction.
CoRR, 2024

3D-VLA: A 3D Vision-Language-Action Generative World Model.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

2023
Boundary Vorticity Estimates for Navier-Stokes and Application to the Inviscid Limit.
SIAM J. Math. Anal., August, 2023

A fast Wigner Hough transform algorithm for parameter estimation of low probability of intercept radar polyphase coded signals.
IET Signal Process., May, 2023

Radar specific emitter identification based on open-selective kernel residual network.
Digit. Signal Process., April, 2023

Forecasting Short-Term Passenger Flow of Subway Stations Based on the Temporal Pattern Attention Mechanism and the Long Short-Term Memory Network.
ISPRS Int. J. Geo Inf., January, 2023

2022
A Simple Duality Proof for Wasserstein Distributionally Robust Optimization.
CoRR, 2022

2021
A Dense 3-D Point Cloud Measurement Based on 1-D Background-Normalized Fourier Transform.
IEEE Trans. Instrum. Meas., 2021

2019
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application.
IET Circuits Devices Syst., 2019

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.
Sci. China Inf. Sci., 2019

2018
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter.
IEICE Electron. Express, 2017

A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015


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