Jinan Lou

According to our database1, Jinan Lou authored at least 13 papers between 1997 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Post sign-off leakage power optimization.
Proceedings of the 48th Design Automation Conference, 2011

2004
Crosstalk-Aware Placement.
IEEE Des. Test Comput., 2004

2003
Cross talk driven placement.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Hierarchical buffered routing tree generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Estimating routing congestion using probabilistic analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
Estimating routing congestion using probabilistic analysis.
Proceedings of the 2001 International Symposium on Physical Design, 2001

1999
An integrated logical and physical design flow for deep submicron circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Concurrent logic restructuring and placement for timing closure.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A simultaneous routing tree construction and fanout optimization algorithm.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together.
Proceedings of the 35th Conference on Design Automation, 1998

An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits.
Proceedings of the ASP-DAC '98, 1998

1997
An exact solution to simultaneous technology mapping and linear placement problem.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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