Jin-Yub Lee
According to our database1,
Jin-Yub Lee
authored at least 13 papers
between 2008 and 2024.
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Bibliography
2024
13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 3.0 Gb/s/pin 4<sup>th</sup> generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021
A 512Gb 3b/Cell 7<sup>th</sup> -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2019
Machine Learning-Based Automatic Generation of eFuse Configuration in NAND Flash Chip.
Proceedings of the IEEE International Test Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2008
IEEE J. Solid State Circuits, 2008