Jin-Yi Lin

According to our database, Jin-Yi Lin authored at least 17 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Temperature-Prediction Based Rate-Adjusted Time and Space Mapping Algorithm for 3D CNN Accelerator Systems.

Jin-Yi Lin, Shu-Yen Lin

IEEE Trans. Computers, October, 2023

iCAPD: A Deep Learning-Based Monitoring System for Continuous Ambulatory Peritoneal Dialysis.

Ming-Che Chen, Hsin-Hsu Chou, Hsiag-Chun Chen, Jin-Yi Lin, Ren-Guei Hsu, Jia-Xiang Chen, Yu-Tse Lee, Jung-Yao Zhuo, Wan-Jung Chang, Yang-Kun Ou

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

A Weightlifting Clean and Jerk Team Formation Model by Considering Barbell Trajectory and LSTM Neural Network.

Jin-Yi Lin, Yan-Ren Ban, Ching-Ting Hsu, Wei Hua Ho, Pao-Hung Chung

Proceedings of the Artificial Intelligence in HCI, 2023

2019

Dynamic Thermal-Aware Inter-Layer Perpendicular Downward Mapping for Three-Dimensional Convolutional Neural Network Accelerator.

Shu-Yen Lin, Jin-Yi Lin

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

2017

A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS.

Jin-Yi Lin, Chih-Cheng Hsieh

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Thermal- and Performance-Aware Address Mapping for the Multi-Channel Three-Dimensional DRAM Systems.

Shu-Yen Lin, Jin-Yi Lin

IEEE Access, 2017

2016

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching.

Pei-Chen Lee, Jin-Yi Lin, Chih-Cheng Hsieh

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A passband lock loop circuit system for band pass filter.

Hung-Wen Lin, Jin-Yi Lin

Proceedings of the International SoC Design Conference, 2016

A reconfigurable near-data systolic array accelerator for the three-dimensional DRAM systems.

Shu-Yen Lin, Jin-Yi Lin, Cheng-Hung Lin

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2015

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS.

Jin-Yi Lin, Chih-Cheng Hsieh

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An 8-bit column-shared SAR ADC for CMOS image sensor applications.

Jin-Yi Lin, Kwuang-Han Chang, Chen-Che Kao, Shih-Chin Lo, Yan-Jiun Chen, Pei-Chen Lee, Chi-Hui Chen, Chin Yin, Chih-Cheng Hsieh

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Real-time data compression for thermal-controlled three-dimensional DRAM systems.

Shu-Yen Lin, Jin-Yi Lin, Kai-Wei Chang, Cheng-Hung Huang

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014

A low-area digitalized channel selection filter for DSRC system.

Hung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Thermal-aware architecture and mapping for multi-channel three-dimensional DRAM systems.

Shu-Yen Lin, Jin-Yi Lin

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2012

A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching.

Hsin-Yuan Huang, Jin-Yi Lin, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai, Chin-Fong Chiu

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Robot Pose and Velocity Estimation Using a Binocular Vision.

Yin-Tien Wang, Shi-Hao Wang, Ying-Chieh Feng, Jin-Yi Lin

Proceedings of the Next Wave in Robotics - 14th FIRA RoboWorld Congress, 2011

A new CMOS image sensor readout structure for 3D integrated imagers.

Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh, Ka-Yi Yeh, Chung-Chi Jim Li

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011