Jin Yang

According to our database, Jin Yang authored at least 43 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Correct-by-Construction Design of Custom Accelerator Microarchitectures.

Jin Yang, Zhenkun Yang, Jeremy Casas, Sandip Ray

IEEE Trans. Computers, January, 2024

2023

Towards A Correct-by-Construction FHE Model.

Zhenkun Yang, Wen Wang, Jeremy Casas, Pasquale Cocchini, Jin Yang

IACR Cryptol. ePrint Arch., 2023

High-level Synthesis for Domain Specific Computing.

Hanchen Ye, HyeGang Jun, Jin Yang, Deming Chen

Proceedings of the 2023 International Symposium on Physical Design, 2023

An Automated Verification Framework for HalideIR-Based Compiler Transformations.

Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design.

Jin Yang, Jeremy Casas, Zhenkun Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Towards A Formally Verified Fully Homomorphic Encryption Compute Engine.

Jeremy Casas, Zhenkun Yang, Wen Wang, Jin Yang, Adwait Godbole

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

An Equivalence Checking Framework for Agile Hardware Design.

Yanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Mining Patterns From Concurrent Execution Traces.

Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Accelerator design with decoupled hardware customizations: benefits and challenges: invited.

Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors.

David Shia, Jin Yang

Microelectron. J., 2021

A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration.

Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang

CoRR, 2021

Model Synthesis for Communication Traces of System-on-Chip Designs.

Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang

CoRR, 2021

A Comparative Study of Specification Mining Methods for SoC Communication Traces.

Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Mining Message Flows from System-on-Chip Execution Traces.

Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Model Synthesis for Communication Traces of System Designs.

Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.

Yuting Cao, Hao Zheng, Sandip Ray, Jin Yang

CoRR, 2020

Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs.

Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

UEFI Firmware Fuzzing with Simics Virtual Platform.

Zhenkun Yang, Yuriy Viktorov, Jin Yang, Jiewen Yao, Vincent Zimmer

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2017

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.

Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

Protocol-guided analysis of post-silicon traces under limited observability.

Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Correctness and security at odds: post-silicon validation of modern SoC designs.

Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

From visual to logical formalisms for SoC validation.

Ranan Fraer, Doron Keren, Zurab Khasidashvili, Alexander Novakovsky, Avi Puder, Eli Singerman, Eran Talmor, Moshe Y. Vardi, Jin Yang

Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Security of SoC firmware load protocols.

Sava Krstic, Jin Yang, David W. Palmer, Randy B. Osborne, Eran Talmor

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2012

Formal-Analysis-Based Trace Computation for Post-Silicon Debug.

Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang

IEEE Trans. Very Large Scale Integr. Syst., 2012

SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience.

Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang

IEEE Des. Test Comput., 2012

2010

Optimizing equivalence checking for behavioral synthesis.

Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Formal Verification for High-Assurance Behavioral Synthesis.

Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Yang

Proceedings of the Automated Technology for Verification and Analysis, 2009

2008

BackSpace: Formal Analysis for Post-Silicon Debug.

Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang

Proceedings of the Formal Methods in Computer-Aided Design, 2008

Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation.

Yan Chen, Fei Xie, Jin Yang

Proceedings of the 45th Design Automation Conference, 2008

2007

Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation.

Yan Chen, Yujing He, Fei Xie, Jin Yang

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006

Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.

William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Maximal Models of Assertion Graph in GSTE.

Guowu Yang, Jin Yang, Xiaoyu Song, Fei Xie

Proceedings of the Theory and Applications of Models of Computation, 2006

Verification Challenges and Opportunities in the New Era of Microprocessor Design.

Jin Yang

Proceedings of the Automated Technology for Verification and Analysis, 2006

2005

Implication of assertion graphs in GSTE.

Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Tightly integrate dynamic verification with formal verification: a GSTE based approach.

Jin Yang, Avi Puder

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Partitioned model checking from software specifications.

Xiushan Feng, Alan J. Hu, Jin Yang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Quantum logic synthesis by symbolic reachability analysis.

William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski

Proceedings of the 41th Design Automation Conference, 2004

Compositional Specification and Model Checking in GSTE.

Jin Yang, Carl-Johan H. Seger

Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003

Introduction to generalized symbolic trajectory evaluation.

Jin Yang, Carl-Johan H. Seger

IEEE Trans. Very Large Scale Integr. Syst., 2003

Reasoning about GSTE Assertion Graphs.

Alan J. Hu, Jeremy Casas, Jin Yang

Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002

GSTE through a case study.

Jin Yang, Amit Goel

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Generalized Symbolic Trajectory Evaluation - Abstraction in Action.

Jin Yang, Carl-Johan H. Seger

Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

2000

Lazy symbolic model checking.

Jin Yang, Andreas Tiemeyer

Proceedings of the 37th Conference on Design Automation, 2000