Jin-Tai Yan

IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Design and analysis of sum-prediction adder.

[BibT_eX]

[DOI]

Integr., 2024

2023

Layer-Minimization-Oriented GNR Area Routing.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022

Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Fuzzy-Clustering-Based Circular Topological Via Minimization in PCB Designs.

[BibT_eX]

[DOI]

IEEE Trans. Fuzzy Syst., 2021

Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Efficient Standard-Cell Legalization for Minimization of Total Movement.

[BibT_eX]

[DOI]

Po-Yuan Huang

Chia-Hsun Yen

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Delay-Constrained GNR Routing for Layer Minimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

Construction of Obstacle-Avoiding Delay-Driven GNR Routing Tree.

[BibT_eX]

[DOI]

Po-Yuan Huang

Chien-Yi Wang

Proceedings of the 2020 IEEE Region 10 Conference, 2020

2019

Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Single-Layer GNR Routing for Minimization of Bending Delay.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Construction of Delay-Driven GNR Routing Tree.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018

Direction-Constrained Rectangle Escape Routing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

On-Chip Optical Channel Routing for Signal Loss Minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Feasible Assignment of Micro-Bumps in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017

Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

One-Sided Net Untangling With Internal Detours for Bus Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016

Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Cell-aware MBFF utilization for clock power reduction.

[BibT_eX]

[DOI]

Meng-Tian Chen

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Single-layer obstacle-aware routing for substrate interconnections.

[BibT_eX]

[DOI]

Integr., 2015

Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs.

[BibT_eX]

[DOI]

Integr., 2015

Length-constrained escape routing of differential pairs.

[BibT_eX]

[DOI]

Integr., 2015

2014

Fault-tolerant analysis of TMR design with noise-aware logic.

[BibT_eX]

[DOI]

Integr., 2014

Feasible region assignment of routing nets in single-layer routing.

[BibT_eX]

[DOI]

Yu-Jen Tseng

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Efficient micro-bump assignment for RDL routing in 3DICs.

[BibT_eX]

[DOI]

Yu-Jen Tseng

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Routability-constrained multi-bit flip-flop construction for clock power reduction.

[BibT_eX]

[DOI]

Integr., 2013

Post-layout redundant wire insertion for fixing min-delay violations.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Timing-constrained replacement using spare cells for design changes.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

New optimal layer assignment for bus-oriented escape routing.

[BibT_eX]

[DOI]

Integr., 2012

Resource-constrained link insertion for delay reduction.

[BibT_eX]

[DOI]

Integr., 2012

Direction-constrained layer assignment for rectangle escape routing.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International SOC Conference, 2012

Efficient assignment of inter-die signals for die-stacking SiP design.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Utilization of multi-bit flip-flops for clock power reduction.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Post-layout OPE-predicted redundant wire insertion for clock skew minimization.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Top-down-based symmetrical buffered clock routing.

[BibT_eX]

[DOI]

Ming-Chien Huang

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Density-reduction-oriented layer assignment for rectangle escape routing.

[BibT_eX]

[DOI]

Jun-Min Chung

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

IO connection assignment and RDL routing for flip-chip designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Simultaneous escape routing based on routability-driven net ordering.

[BibT_eX]

[DOI]

Tung-Yen Sung

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Obstacle-aware length-matching bus routing.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

Pre-assignment RDL routing via extraction of maximal net sequence.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Timing-constrained I/O buffer placement for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Thermal via planning for temperature reduction in 3D ICs.

[BibT_eX]

[DOI]

Yu-Cheng Chang

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Routability-driven RDL routing with pin reassignment.

[BibT_eX]

[DOI]

Ke-Chyuan Chen

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Low-cost low-power bypassing-based multiplier design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Width-constrained wire sizing for non-tree interconnections.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Routability-driven flip-flop merging process for clock power reduction.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Ordered escape routing via routability-driven pin assignment.

[BibT_eX]

[DOI]

Chung-Wei Ke

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Resource-constrained timing-driven link insertion for critical delay reduction.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Two-sided single-detour untangling for bus routing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Obstacle-aware longest path using rectangular pattern detouring in routing grids.

[BibT_eX]

[DOI]

Ming-Ching Jhong

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Routability-driven partitioning-based IO assignment for flip-chip designs.

[BibT_eX]

[DOI]

Kai-Ping Lu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Low-power multiplier design with row and column bypassing.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Accurate Transformation-based Timing Analysis for RC Non-tree Circuits.

[BibT_eX]

[DOI]

Hsing-Lin Ko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Redundant wire insertion for yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

RDL pre-assignment routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

IO connection assignment and RDL routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Thermal-driven white space redistribution for block-level floorplans.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Flexible escape routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Timing-constrained yield-driven redundant via insertion.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Electromigration-aware rectilinear Steiner tree construction for analog circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Timing-driven multi-layer Steiner tree construction with obstacle avoidance.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity.

[BibT_eX]

[DOI]

Ming-Yuen Wu

Proceedings of the 2007 IEEE International SOC Conference, 2007

Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.

[BibT_eX]

[DOI]

Ming-Yuen Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance.

[BibT_eX]

[DOI]

Shi-Qin Huang

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Routability-Driven Track Routing for Coupling Capacitance Reduction.

[BibT_eX]

[DOI]

Kuen-Ming Lin

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.

[BibT_eX]

[DOI]

Kai-Ping Lin

Yue-Fong Luo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Optimal shielding insertion for inductive noise avoidance.

[BibT_eX]

[DOI]

Kuen-Ming Lin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Multilevel timing-constrained full-chip routing in hierarchical quad-grid model.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Timing-constrained yield-driven wire sizing for critical area minimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Area-Driven White Space Distribution for Detailed Floorplan Design.

[BibT_eX]

[DOI]

Ming-Yuen Wu

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Optimal Network Analysis in Hierarchical Power Quad-Grids.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Width and Timing-Constrained Wire Sizing for Critical Area Minimization.

[BibT_eX]

[DOI]

Shi-Qin Huang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Timing-Constrained Flexibility-Driven Routing Tree Construction.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points.

[BibT_eX]

[DOI]

Tzu-Ya Wang

Yu-Cheng Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Wiring area optimization in floorplan-aware hierarchical power grids.

[BibT_eX]

[DOI]

Chia-Wei Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.

[BibT_eX]

[DOI]

Kai-Ping Lin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Probabilistic congestion prediction in hierarchical quad-grid model.

[BibT_eX]

[DOI]

Chia-Wei Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Floorplan-aware Steiner tree reconstruction for optimal buffer insertion.

[BibT_eX]

[DOI]

Tzu-Ya Wang

Proceedings of the 12th IEEE International Conference on Electronics, 2005

LB-packing-based floorplan design on DBL representation.

[BibT_eX]

[DOI]

Kai-Ping Lin

Yue-Fong Luo

Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004

Timing-constrained congestion-driven global routing.

[BibT_eX]

[DOI]

Shun-Hua Lin

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002

Printed circuit board routing and package layout codesign.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000

Three-layer bubble-sorting-based nonManhattan channel routing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

1999

An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement.

[BibT_eX]

[DOI]

VLSI Design, 1999

Routability Crossing Distribution and Floating Pin Assignment for <i>T</i>-type Junction Region.

[BibT_eX]

[DOI]

VLSI Design, 1999

An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Routing Space Estimation and Assignment for Macro-Cell Placement.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1998

1996

An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment.

[BibT_eX]

[DOI]

VLSI Design, 1996

Minimizing the number of switchboxes for region definition and ordering assignment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A simple yet effective genetic approach for the orientation assignment on cell-based layout.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

A new fuzzy-clustering-based approach for two-way circuit partitioning.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Region definition and ordering assignment with the minimization of the number of switchboxes.

[BibT_eX]

[DOI]

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A Fuzzy Clustering Algorithm for Graph Bisection.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1994

Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Routability crossing distribution and floating terminal assignment of T-type junction region.

[BibT_eX]

[DOI]