Jin-Mei Lai

Shuai Zhou

IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Accurate Area Model for FPGA Circuits at Advanced Technologies.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator.

[BibT_eX]

[DOI]

Jiabao Gao

IEEE Trans. Circuits Syst. II Express Briefs, 2022

3-D Auxiliary Classifier GAN for Hyperspectral Anomaly Detection via Weakly Supervised Learning.

[BibT_eX]

[DOI]

IEEE Geosci. Remote. Sens. Lett., 2022

AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design.

[BibT_eX]

[DOI]

Integr., 2022

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure.

[BibT_eX]

[DOI]

Zhengjie Li

Jiabao Gao

IEICE Trans. Inf. Syst., 2021

FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2021

TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference.

[BibT_eX]

[DOI]

Jiabao Gao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A Tile-based Interconnect Model for FPGA Architecture Exploration.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

INTB: A New FPGA Interconnect Model for Architecture Exploration.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

HRAE: Hardware-assisted Randomization against Adversarial Example Attacks.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Stochastic Loss Function.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019

An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Analytical-based Hybrid Algorithm for FPGA Placement.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Research on the impact of different benchmark circuits on the representative path in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Design and implementation of Serial ATA pbysical layer on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Research on Area Modeling Methodology for FPGA Interconnect Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

An FPGA-based log-structure Flash memory system for space exploration.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Low-delay Configurable Register for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Balance of memory footprint and runtime for high-density routing in large-scale FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Web-based Waveform Viewer for BR0101 Chip Testing Platform.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Polymorphic Circuit Interoperability Framework.

[BibT_eX]

[DOI]

Timothy Dunlap

Gang Qu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Design of a power efficient self-adaptive LVDS driver.

[BibT_eX]

[DOI]

Hanyang Xu

IEICE Electron. Express, 2018

A SA-based parallel method for FPGA placement.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

2017

Flux balance analysis predicts Warburg-like effects of mouse hepatocyte deficient in miR-122a.

[BibT_eX]

[DOI]

PLoS Comput. Biol., 2017

FPGA-based convolution neural network for traffic sign recognition.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A deep research on the chip verification platform based on network.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Prototyping design of a flexible DSP block with pipeline structure for FPGA.

[BibT_eX]

[DOI]

Hanyang Xu

IEICE Electron. Express, 2016

A universal automatic on-chip measurement of FPGA's internal setup and hold times.

[BibT_eX]

[DOI]

Yuanlong Xiao

IEICE Electron. Express, 2016

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Design and implementation of clock network for nanometer FPGA.

[BibT_eX]

[DOI]

Lei Li

IEICE Electron. Express, 2015

A power efficient current-mode differential driver for FPGAs.

[BibT_eX]

[DOI]

Yuanlong Xiao

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Iterative optimization algorithm for sound localization.

[BibT_eX]

[DOI]

Fang Sun

Jin-Mei Lai

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

An Architecture Independent Packing Method for LUT-based Commercial FPGA.

[BibT_eX]

[DOI]

A. E. A. Almaini

J. Comput., 2014

Novel FPGA clock network with low latency and skew (abstract only).

[BibT_eX]

[DOI]

Lei Li

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013

Optimisation of Mixed Polarity Reed-Muller Functions.

[BibT_eX]

[DOI]

J. Softw., 2013

Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions.

[BibT_eX]

[DOI]

Jiarong Tong

J. Comput., 2013

A hierarchical parallel evolvable hardware based on network on chip.

[BibT_eX]

[DOI]

Jun Rong Wang

Dan Wang

Jin-Mei Lai

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A novel net-partition-based multithread FPGA routing method.

[BibT_eX]

[DOI]

Chun Zhu

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD.

[BibT_eX]

[DOI]

Jiarong Tong

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel multithread routing method for FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

FPGA bitstream compression and decompression using LZ and golomb coding (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

The timing control design of 65nm block RAM in FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A high throughput FPGA embedded DSP architecture design.

[BibT_eX]

[DOI]

Hanyang Xu

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Improved unified interconnect unit for high speed and scalable FPGA.

[BibT_eX]

[DOI]

Lei Li

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Weight-based FPGA placement algorithm with wire effect considered.

[BibT_eX]

[DOI]

Huagang Li

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A high-resolution TDC implemented in a 90nm process FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

A novel memristor-based rSRAM structure for multiple-bit upsets immunity.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

A novel full coverage test method for CLBs in FPGA (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Finite State Machine Synthesis Based on Relay-Based Algorithm.

[BibT_eX]

[DOI]

M. Yang

Hongying Xu

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

FPGA Interconnect Architecture Exploration Based on a Statistical Model.

[BibT_eX]

[DOI]

Zhen Wang

Ding Xie

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

The design and verification of SEU-hardened configurable DFF.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA interconnect timing library based on the statistical method.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Research on design method of scalable Configurable IP Core.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2009

Inferring a transcriptional regulatory network of the cytokinesis-related genes by network component analysis.

[BibT_eX]

[DOI]

BMC Syst. Biol., 2009

POINeT: protein interactome with sub-network analysis and hub prioritization.

[BibT_eX]

[DOI]

BMC Bioinform., 2009

Self-adaptive evolution of complex logic circuits.

[BibT_eX]

[DOI]

Xiaoxuan She

Proceedings of the 2009 IEEE Workshop on Evolvable and Adaptive Hardware, 2009

A novel minloop SB design to improve FPGA routability.

[BibT_eX]

[DOI]

JIanDe Yu