Jin He
Orcid: 0000-0002-2261-4914Affiliations:
- Peking University, Shenzhen SOC Key Laboratory, China
According to our database1,
Jin He
authored at least 27 papers
between 2001 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review.
IEEE Access, 2023
2020
Synthesis Design of Equal-Ripple and Quasi-Elliptic Wideband BPFs With Independently Reconfigurable Lower Passband Edge.
IEEE Access, 2020
2019
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
2017
IEEE J. Solid State Circuits, 2017
2013
Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions.
IEICE Trans. Electron., 2013
2012
ACM J. Emerg. Technol. Comput. Syst., 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A physical based model to predict performance degradation of FinFET accounting for interface state distribution effect due to hot carrier injection.
Microelectron. Reliab., 2011
Terahertz spectroscopic uncertainty analysis for explosive mixture components determination using multi-objective micro-genetic algorithm.
Adv. Eng. Softw., 2011
A new nonlinear parameterized model order reduction technique combining the interpolation method and Proper Orthogonal Decomposition.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect.
Microelectron. Reliab., 2010
Temperature dependence of the interface state distribution due to hot carrier effect in FinFET device.
Microelectron. Reliab., 2010
J. Low Power Electron., 2010
2009
Microelectron. Reliab., 2009
An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transport.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2006
A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
2004
A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration.
Microelectron. Reliab., 2003
Microelectron. Reliab., 2003
2002
Application of forward gated-diode R-G current method in extracting F-N stress-induced interface traps in SOI NMOSFETs.
Microelectron. Reliab., 2002
2001
Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique.
Microelectron. Reliab., 2001