Jim Tschanz

According to our database, Jim Tschanz authored at least 8 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2023

A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS.

Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Innovations for Intelligent Edge.

Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2020

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit.

Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, C. Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.

Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2017

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS.

Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015

A fully integrated charge sharing active decap scheme for power supply noise suppression.

Ahmed M. Ammar, Rafik Guindi, Ethan Shih, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2013

Minimum supply voltage for sequential logic circuits in a 22nm technology.

Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012

A 22nm dynamically adaptive clock distribution for voltage droop tolerance.

Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz

Proceedings of the Symposium on VLSI Circuits, 2012