Jim D. Garside
Orcid: 0000-0001-8812-4742Affiliations:
- University of Manchester, UK
According to our database1,
Jim D. Garside
authored at least 80 papers
between 1992 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021
2020
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks.
Simul. Model. Pract. Theory, 2020
IEEE Access, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application.
IEEE Trans. Biomed. Circuits Syst., 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2017
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2017
HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017
Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
ACM Trans. Archit. Code Optim., 2016
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
On-chip order-exploiting routing table minimization for a multicast supercomputer network.
Proceedings of the 17th IEEE International Conference on High Performance Switching and Routing, 2016
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016
Proceedings of the 16th International Conference on Application of Concurrency to System Design, 2016
2015
Analysis of FPGA and software approaches to simulate unconventional computer architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes.
Microprocess. Microsystems, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
2013
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
J. Parallel Distributed Comput., 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012
2011
ACM J. Emerg. Technol. Comput. Syst., 2011
2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
2007
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Modernization of teaching in embedded systems design - an international collaborative project.
IEEE Trans. Educ., 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
Microprocess. Microsystems, 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
2001
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994
1993
A micropipelined ARM.
Proceedings of the VLSI 93, 1993
A CMOS VLSI Implementation of an Asynchronous ALU.
Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992