Jihye Kim

Orcid: 0000-0002-9362-0836

Affiliations:
  • Samsung Electronics, Hwaseoung, South Korea
  • Yonsei University, Seoul, South Korea (PhD 2022)


According to our database1, Jihye Kim authored at least 11 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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2020
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
STRAIT: Self-Test and Self-Recovery for AI Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

2022
ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks.
Sensors, 2021

Reconfigurable Scan Architecture for High Diagnostic Resolution.
IEEE Access, 2021

2020
Fine-Grained Defect Diagnosis for CMOL FPGA Circuits.
IEEE Access, 2020

Memory-like Defect Diagnosis for CMOL FPGAs.
Proceedings of the International SoC Design Conference, 2020

2019
Test-Friendly Data-Selectable Self-Gating (DSSG).
IEEE Trans. Very Large Scale Integr. Syst., 2019

Transition-delay Test Methodology for Designs with Self-gating.
Proceedings of the 2019 International SoC Design Conference, 2019

A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density.
Proceedings of the 2019 International SoC Design Conference, 2019

2014
Test Compression Improvement with EDT Channel Sharing in SoC Designs.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

2002
An Efficient On-Line Monitoring BIST for Remote Service System.
Proceedings of the Advanced Internet Services and Applications, 2002


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