Jihang Gao

According to our database1, Jihang Gao authored at least 8 papers between 2022 and 2024.

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Bibliography

2024
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


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