Jih Ren Goh

According to our database, Jih Ren Goh authored at least 4 papers between 2014 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop.

Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Jih Ren Goh, C. Thomas Gray

IEEE J. Solid State Circuits, 2022

2017

A low power duobinary voltage mode transmitter.

Ming-Hung Chien, Yen-Long Lee, Jih Ren Goh, Soon-Jyh Chang

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2015

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits.

Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang

Proceedings of the VLSI Design, Automation and Test, 2015

2014

An area- and power-efficient half-rate clock and data recovery circuit.

Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, Chung-Ming Huang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014