Jih-Nung Lee

Orcid: 0000-0003-4805-4350

According to our database¹, Jih-Nung Lee authored at least 15 papers between 2003 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2023

CNN-Based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022

Methodology of Generating Timing-Slack-Based Cell-Aware Tests.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

CNN-based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

Layout-Based Dual-Cell-Aware Tests.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

A Model-Based-Random-Forest Framework for Predicting V<sub>t</sub> Mean and Variance Based on Parallel I<sub>d</sub> Measurement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Methodology of generating dual-cell-aware tests.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015

Case study of process and design performance debugging with Digital Speed Sensor.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Physical-aware systematic multiple defect diagnosis.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2014

2013

Case study of yield learning through in-house flow of volume diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2009

A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

2003

Fault Pattern Oriented Defect Diagnosis for Memories.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Jih-Nung Lee

Timeline

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