Jiexian Ge
According to our database1,
Jiexian Ge
authored at least 2 papers
between 2019 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead.
Proceedings of the 13th IEEE International Conference on ASIC, 2019