Jieru Zhao
Orcid: 0000-0001-8211-2812
According to our database1,
Jieru Zhao
authored at least 44 papers
between 2017 and 2024.
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Bibliography
2024
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition.
ACM Trans. Reconfigurable Technol. Syst., December, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
HGS-Mapping: Online Dense Mapping Using Hybrid Gaussian Representation in Urban Scenes.
IEEE Robotics Autom. Lett., November, 2024
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs.
ACM Trans. Reconfigurable Technol. Syst., September, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
SparseTem: Boosting the Efficiency of CNN-Based Video Encoders by Exploiting Temporal Continuity.
CoRR, 2024
Inf-MLLM: Efficient Streaming Inference of Multimodal Large Language Models on a Single GPU.
CoRR, 2024
CoRR, 2024
CoRR, 2024
The CAP Principle for LLM Serving: A Survey of Long-Context Large Language Model Serving.
CoRR, 2024
CoRR, 2024
HGS-Mapping: Online Dense Mapping Using Hybrid Gaussian Representation in Urban Scenes.
CoRR, 2024
PAS: Towards Accurate and Efficient Federated Learning with Parameter-Adaptive Synchronization.
Proceedings of the 32nd IEEE/ACM International Symposium on Quality of Service, 2024
A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
O <sub>2</sub>V-Mapping: Online Open-Vocabulary Mapping with Neural Implicit Representation.
Proceedings of the Computer Vision - ECCV 2024, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Frontiers Comput. Sci., October, 2023
PAC: Preference-Aware Co-location Scheduling on Heterogeneous NUMA Architectures To Improve Resource Utilization.
Proceedings of the 37th International Conference on Supercomputing, 2023
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
Skadi: Building a Distributed Runtime for Data Systems in Disaggregated Data Centers.
Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 2023
SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2023
SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
CSC: Collaborative System Configuration for I/O-Intensive Applications in Multi-Tenant Clouds.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Characterizing and orchestrating VM reservation in geo-distributed clouds to improve the resource efficiency.
Proceedings of the 13th Symposium on Cloud Computing, SoCC 2022, 2022
2021
Enable simultaneous DNN services based on deterministic operator overlap and precise latency prediction.
Proceedings of the International Conference for High Performance Computing, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2019
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017