Jieqiong Du
Orcid: 0000-0001-9185-2353
According to our database1,
Jieqiong Du
authored at least 11 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
2018
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2018
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
2017
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection.
IEEE J. Solid State Circuits, 2017
2016
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016