Jieming Yin
Orcid: 0009-0008-2878-1853
According to our database1,
Jieming Yin
authored at least 27 papers
between 2011 and 2024.
Collaborative distances:
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Bibliography
2024
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
2023
ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators.
CoRR, 2023
Proceedings of the 32nd USENIX Security Symposium, 2023
QuCT: A Framework for Analyzing Quantum Circuit by Extracting Contextual and Topological Features.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
CompoundEye: A 0.24-4.17 TOPS Scalable Multi-Node DNN Processor for Image Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
COLA: Orchestrating Error Coding and Learning for Robust Neural Network Inference Against Hardware Defects.
Proceedings of the International Conference on Machine Learning, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Des. Test, 2022
CryptoGCN: Fast and Scalable Homomorphically Encrypted Graph Convolutional Network Inference.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
2021
Improving Address Translation in Multi-GPUs via Sharing and Spilling aware TLB Design.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Integr., 2019
Northup: Divide-and-Conquer Programming in Systems with Heterogeneous Memories and Processors.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019
2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2014
Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
2012
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011