Jielun Tan
According to our database1,
Jielun Tan
authored at least 9 papers
between 2019 and 2022.
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Bibliography
2022
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
2021
Proceedings of the ACM/IEEE Workshop on Computer Architecture Education, 2021
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA.
Proceedings of the SIGCSE '21: The 52nd ACM Technical Symposium on Computer Science Education, 2021
2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019