Jie Zhou

According to our database, Jie Zhou authored at least 29 papers between 2007 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Hyperspectral image classification via kernel extreme learning machine using local receptive fields.

Qi Lv, Xin Niu, Yong Dou, Yueqing Wang, Jiaqing Xu, Jie Zhou

Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2014

CuSora: Real-time software radio using multi-core graphics processing unit.

Rongchun Li, Yong Dou, Jie Zhou, Lin Deng, Shi Wang

J. Syst. Archit., 2014

Design and Implement of High Performance Crypto Coprocessor.

Shi-Ce Ni, Yong Dou, Kai Chen, Jie Zhou

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Efficient Parallel Interference Cancellation MIMO Detector for Software Defined Radio on GPUs.

Rongchun Li, Yong Dou, Jie Zhou, Chen Chen

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Transpose-free variable-size FFT accelerator based on-chip SRAM.

Lei Guo, Yuhua Tang, Yuanwu Lei, Yong Dou, Jie Zhou

IEICE Electron. Express, 2014

2013

FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic.

Yuanwu Lei, Yong Dou, Yazhuo Dong, Jie Zhou, Fei Xia

J. Supercomput., 2013

VLIW coprocessor for IEEE-754 quadruple-precision elementary functions.

Yuanwu Lei, Yong Dou, Lei Guo, Jinbo Xu, Jie Zhou, Yazhuo Dong, Hongjian Li

ACM Trans. Archit. Code Optim., 2013

From WiFi to WiMAX: Efficient GPU-based Parameterized Transceiver across Different OFDM Protocols.

Rongchun Li, Yong Dou, Jie Zhou, Baofeng Li, Jinbo Xu

KSII Trans. Internet Inf. Syst., 2013

Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access.

Lei Guo, Yuhua Tang, Yong Dou, Yuanwu Lei, Meng Ma, Jie Zhou

IEICE Trans. Inf. Syst., 2013

A multi-standard efficient column-layered LDPC decoder for Software Defined Radio on GPUs.

Rongchun Li, Jie Zhou, Yong Dou, Song Guo, Dan Zou, Shi Wang

Proceedings of the 14th IEEE Workshop on Signal Processing Advances in Wireless Communications, 2013

2012

A malicious code detection method based on statistical analysis.

Yunlong Wu, Chen Chen, Huiquan Wang, Jie Zhou, Xinhai Xu

Proceedings of the 9th International Conference on Fuzzy Systems and Knowledge Discovery, 2012

A self-organizing and self-adaptive French flag Organism based on lateral activation model.

Jiaqing Xu, Qi Lv, Jie Zhou, Yong Dou

Proceedings of the IEEE Congress on Evolutionary Computation, 2012

2011

FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic.

Yuanwu Lei, Yong Dou, Jie Zhou

IEICE Trans. Inf. Syst., 2011

A high-throughput reconfigurable Viterbi decoder.

Rongchun Li, Yong Dou, Jie Zhou, Guo-Qing Lei

Proceedings of the 2011 International Conference on Wireless Communications & Signal Processing, 2011

Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA.

Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic.

Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

FPGA Implementation of Variable-Precision Floating-Point Arithmetic.

Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou

Proceedings of the Advanced Parallel Processing Technologies - 9th International Symposium, 2011

2010

A Unified Co-Processor Architecture for Matrix Decomposition.

Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni

J. Comput. Sci. Technol., 2010

FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.

Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen

Proceedings of the 24th International Conference on Supercomputing, 2010

2009

FPGA accelerating three QR decomposition algorithms in the unified pipelined framework.

Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.

Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang

Proceedings of the FCCM 2009, 2009

A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.

Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang

Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009

2008

Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme.

Jinbo Xu, Yong Dou, Jie Zhou

Proceedings of The 2008 IEEE International Conference on Networking, 2008

Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA.

Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei

Proceedings of the International Conference on Embedded Software and Systems, 2008

Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.

Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong

Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008

Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.

Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong

Proceedings of the Reconfigurable Computing: Architectures, 2008

Multi-access memory architecture for image applications with multiple interested regions.

Jinbo Xu, Yong Dou, Jie Zhou

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

FPGA SAR Processor with Window Memory Accesses.

Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.

Yazhuo Dong, Yong Dou, Jie Zhou

Proceedings of the Reconfigurable Computing: Architectures, 2007