Jie Zhang

According to our database, Jie Zhang authored at least 16 papers between 2008 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.

Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.

Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli

ACM J. Emerg. Technol. Comput. Syst., 2014

2013

Carbon nanotube circuits: opportunities and challenges.

Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the Design, Automation and Test in Europe, 2013

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.

Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Carbon Nanotube Robust Digital VLSI.

Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.

Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Robust System Design.

Subhasish Mitra, Hyungmin Cho, Ted Hong, Young Moon Kim, Hsiao-Heng Lee, Larkhoon Leem, Yanjing Li, David Lin, Evelyn Mintarno, Diana Mui, Sung-Boem Park, Nishant Patil, Hai Wei, Jie Zhang

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.

Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Carbon nanotube circuits: Living with imperfections and variations.

Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.

Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra

Proceedings of the 47th Design Automation Conference, 2010

2009

Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.

Jie Zhang, Nishant Patil, Subhasish Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.

Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei

Proceedings of the Design, Automation and Test in Europe, 2009

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.

Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli

Proceedings of the Design, Automation and Test in Europe, 2009

Carbon nanotube circuits in the presence of carbon nanotube density variations.

Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra

Proceedings of the 46th Design Automation Conference, 2009

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.

Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra

Proceedings of the 46th Design Automation Conference, 2009

2008

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.

Jie Zhang, Nishant Patil, Subhasish Mitra

Proceedings of the Design, Automation and Test in Europe, 2008