Jie-Wei Lai

According to our database¹, Jie-Wei Lai authored at least 9 papers between 2005 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2021

Opportunity and Challenge of Chiplet-Based HPC and AIoT.

[BibT_eX]

[DOI]

Jie-Wei Lai

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

2013

A 0.27mm<sup>2</sup> 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS.

[BibT_eX]

[DOI]

Robert Bogdan Staszewski

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications.

[BibT_eX]

[DOI]

Alberto Valdes-Garcia

IEEE Commun. Mag., 2011

2010

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications.

[BibT_eX]

[DOI]

Alberto Valdes-Garcia

IEEE J. Solid State Circuits, 2010

A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications.

[BibT_eX]

[DOI]

Alberto Valdes-Garcia

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS.

[BibT_eX]

[DOI]

Jie-Wei Lai

Alberto Valdes-Garcia

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2005

Large Signal HBT Model and Integrated Circuit Design Using 300-Ghz Indium Phosphide HBT Technology

[BibT_eX]

[DOI]

Jie-Wei Lai

PhD thesis, 2005

Jie-Wei Lai

Timeline

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On csauthors.net:

Bibliography

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