Jie Li

Affiliations:

Harbin Institute of Technology, Microelectronics Center, China

According to our database¹, Jie Li authored at least 19 papers between 2015 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

SET-detection low complexity burst error correction codes for SRAM protection.

[BibT_eX]

[DOI]

Integr., 2024

2022

A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors.

[BibT_eX]

[DOI]

IEEE Access, 2022

2021

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).

[BibT_eX]

[DOI]

Integr., 2021

2020

An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2020

Scheme for periodical concurrent fault detection in parallel CRC circuits.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2020

2019

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

Low redundancy matrix-based codes for adjacent error correction with parity sharing.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A fast and accurate fault injection platform for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Rongsheng Zhang

Liyi Xiao

Jie Li

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A method to estimate cross-section of circuits at RTL levels.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Jie Li

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...