Jie Jiang

According to our database, Jie Jiang authored at least 8 papers between 2007 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

Delay Testing in Nanoscale Technology under Process Variations

Jie Jiang

PhD thesis, 2016

On Optimal Power-Aware Path Sensitization.

Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014

Detection conditions for errors in self-adaptive better-than-worst-case designs.

Ilia Polian, Jie Jiang, Adit D. Singh

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.

Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker

Proceedings of the 14th Latin American Test Workshop, 2013

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator.

Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian

Proceedings of the 22nd Asian Test Symposium, 2013

2012

On the optimality of K longest path generation algorithm under memory constraints.

Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Efficient SAT-Based Search for Longest Sensitisable Paths.

Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2007

Simulating Open-Via Defects.

Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker

Proceedings of the 16th Asian Test Symposium, 2007