Jie Han
Orcid: 0000-0002-8849-4994Affiliations:
- University of Alberta, Department of Electrical and Computer Engineering, Edmonton, AB, Canada
- Northeastern University, Department of Electrical and Computer Engineering, Boston, MA, USA (former)
- Florida University, Department of Electrical and Computer Engineering, Advanced Computing and Information Systems Laboratory, Gainesville, FL, USA (former)
- Delft University of Technology, The Netherlands (PhD 2004)
According to our database1,
Jie Han
authored at least 186 papers
between 2000 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on ualberta.ca
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on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
Learning the Error Features of Approximate Multipliers for Neural Network Applications.
IEEE Trans. Computers, March, 2024
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits.
ACM Trans. Design Autom. Electr. Syst., January, 2024
Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
A Low-Cost and Fault-Tolerant Stochastic Architecture for the Bernsen Algorithm Using Bitstream Correlation.
J. Circuits Syst. Comput., 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
An Approximate Parallel Annealing Ising Machine for Solving Traveling Salesman Problems.
IEEE Embed. Syst. Lett., December, 2023
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems.
IEEE Des. Test, June, 2023
Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators.
J. Comput. Sci. Technol., April, 2023
Guest Editorial Unconventional Computing Techniques for Emerging Technology Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
A stochastic computing architecture for local contrast and mean image thresholding algorithm.
Int. J. Circuit Theory Appl., 2022
Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing.
Int. J. Circuit Theory Appl., 2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated Bifurcation.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the Approximate Computing, 2022
Proceedings of the Approximate Computing, 2022
2021
IEEE Trans. Neural Networks Learn. Syst., 2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Computers, 2021
IET Comput. Digit. Tech., 2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
Absolute Subtraction and Division Circuits Using Uncorrelated Random Bitstreams in Stochastic Computing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Parallel Distributed Syst., 2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications.
Proc. IEEE, 2020
A robust wire crossing design for thermostability and fault tolerance in quantum-dot cellular automata.
Microprocess. Microsystems, 2020
IET Circuits Devices Syst., 2020
A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications.
ACM Comput. Surv., 2020
High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis.
IEEE Access, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation.
IEEE Trans. Computers, 2019
Nano Commun. Networks, 2019
A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology.
CoRR, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Computers, 2018
A stochastic approach for the reliability evaluation of multi-state systems with dependent components.
Reliab. Eng. Syst. Saf., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation.
IEEE Access, 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).
IEEE Trans. Multi Scale Comput. Syst., 2017
IEEE Trans. Computers, 2017
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017
IET Networks, 2017
IEEE Access, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
An efficient hardware design for cerebellar models using approximate circuits: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
2016
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Reliab., 2016
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
Reliability and Criticality Analysis of Communication Networks by Stochastic Computation.
IEEE Netw., 2016
Microelectron. Reliab., 2016
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.
Integr., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
2015
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Reconfigurable Technol. Syst., 2015
A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures.
IEEE Trans. Reliab., 2015
IEEE Trans. Multi Scale Comput. Syst., 2015
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Computers, 2015
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders.
IEEE Trans. Computers, 2015
Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints.
Sci. China Inf. Sci., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
2014
IEEE Trans. Reliab., 2014
A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation.
IEEE Trans. Computers, 2014
J. Comput. Biol., 2014
BMC Syst. Biol., 2014
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A system-level scheme for resistance drift tolerance of a multilevel phase change memory.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A low-power, high-performance approximate multiplier with configurable partial error recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Computers, 2013
IEEE Trans. Computers, 2013
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration.
J. Syst. Archit., 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2012
Stochastic Boolean networks: An efficient approach to modeling gene regulatory networks.
BMC Syst. Biol., 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Microelectron. Reliab., 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Stochastic computational models for accurate reliability evaluation of logic circuits.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
2005
IEEE Des. Test Comput., 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Proceedings of the 17th International Conference on Pattern Recognition, 2004
2003
A Study on Fault-Tolerant Circuits Using Redundancy.
Proceedings of the International Conference on VLSI, 2003
2000
On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000