We stand with Ukraine

We stand with Ukraine

Jie Gu

Affiliations:

Max Linear, Inc., Carlsbad, CA, USA
University of Minnesota, Minneapolis, MN, USA (PhD 2008)

According to our database¹, Jie Gu authored at least 16 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices.

[BibT_eX]

[DOI]

,

Sachin S. Sapatnekar

,

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2021

VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis.

[BibT_eX]

[DOI]

Hadi Esmaeilzadeh

,

Soroush Ghodrati

,

,

,

Andrew B. Kahng

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,

,

Rohan Mahapatra

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Susmita Dey Manasi

,

Edwin Mascarenhas

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Sachin S. Sapatnekar

,

Ravi Varadarajan

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,

Brahmendra Reddy Yatham

,

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2010

Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise.

[BibT_eX]

[DOI]

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IEEE J. Solid State Circuits, 2010

2009

Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2009

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2009

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2009

On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit.

[BibT_eX]

[DOI]

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IEEE J. Solid State Circuits, 2009

Circuit techniques for enhancing the clock data compensation effect under resonant supply noise.

[BibT_eX]

[DOI]

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,

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2008

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.

[BibT_eX]

[DOI]

,

,

Sachin S. Sapatnekar

,

IEEE Trans. Very Large Scale Integr. Syst., 2008

Enhancing <i>beneficial jitter</i> using phase-shifted clock distribution.

[BibT_eX]

[DOI]

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,

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Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007

Sleep transistor sizing and control for resonant supply noise damping.

[BibT_eX]

[DOI]

,

,

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.

[BibT_eX]

[DOI]

,

Sachin S. Sapatnekar

,

Proceedings of the 44th Design Automation Conference, 2007

2006

Modeling and analysis of leakage induced damping effect in low voltage LSIs.

[BibT_eX]

[DOI]

,

,

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Width Quantization Aware FinFET Circuit Design.

[BibT_eX]

[DOI]

,

,

Sachin S. Sapatnekar

,

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Multi-story power delivery for supply noise reduction and low voltage operation.

[BibT_eX]

[DOI]

,

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

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