Jie Chen

According to our database, Jie Chen authored at least 6 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters.

Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters.

Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi

CoRR, 2023

2022

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.

Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini

IEEE J. Solid State Circuits, 2022

2021

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.

Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini

CoRR, 2021

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.

Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster.

Jie Chen, Igor Loi, Luca Benini, Davide Rossi

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020