Jiayi Zhu

According to our database, Jiayi Zhu authored at least 15 papers between 2008 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.

Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

IEEE J. Solid State Circuits, 2017

2016

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.

Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications.

Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, Satoshi Goto

IEEE Trans. Very Large Scale Integr. Syst., 2015

An independent bandwidth reduction device for HEVC VLSI video system.

Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding.

Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder.

Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto

Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Fast SAO estimation algorithm and its VLSI architecture.

Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

2013

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder.

Jiayi Zhu, Dajiang Zhou, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A combined SAO and de-blocking filter architecture for HEVC video decoder.

Jiayi Zhu, Dajiang Zhou, Gang He, Satoshi Goto

Proceedings of the IEEE International Conference on Image Processing, 2013

2012

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications.

Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip.

Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto

IEEE J. Solid State Circuits, 2011

2010

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder.

Xianmin Chen, Peilin Liu, Dajiang Zhou, Jiayi Zhu, Xingguang Pan, Satoshi Goto

IEICE Trans. Electron., 2010

2009

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications.

Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder.

Xianmin Chen, Peilin Liu, Jiayi Zhu, Dajiang Zhou, Satoshi Goto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

An SDRAM controller optimized for high definition video coding application.

Jiayi Zhu, Peilin Liu, Dajiang Zhou

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008