Jiawei Xu

Orcid: 0000-0002-6192-558X

Affiliations:

Fudan University, School of Information Science and Technology, State Key Laboratory of ASIC and System, Shanghai, China

According to our database¹, Jiawei Xu authored at least 18 papers between 2018 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2024

Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

FPGA-Based HPC for Associative Memory System.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., October, 2023

Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022

Edge-Based Collaborative Training System for Artificial Intelligence-of-Things.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2022

Memristor-Based In-Circuit Computation for Trace-Based STDP.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm² Area Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Self-aware distributed deep learning framework for heterogeneous IoT edge devices.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2021

A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

A Smart Dental Health-IoT Platform Based on Intelligent Hardware, Deep Learning, and Mobile Terminal.

[BibT_eX]

[DOI]

IEEE J. Biomed. Health Informatics, 2020

2019

Energy-Aware Workload Allocation for Distributed Deep Neural Networks in Edge-Cloud Continuum.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

Universal and Convenient Optimization Strategies for Three-Terminal Memristors.

[BibT_eX]

[DOI]

IEEE Access, 2018

Optimized Near-Zero Quantization Method for Flexible Memristor Based Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2018

A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A 3D Tiled Low Power Accelerator for Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Jiawei Xu

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