Jiaoyan Chen

Orcid: 0000-0002-0287-951X

Affiliations:
  • TU Delft, Delft, The Netherlands


According to our database1, Jiaoyan Chen authored at least 12 papers between 2010 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits.
Microelectron. Reliab., 2015

Asynchronous Charge Sharing Power Consistent Montgomery Multiplier.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Reliability aware logic synthesis through rewriting.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Robust sub-powered asynchronous logic.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2012
Ultra Low Power Asynchronous Charge Sharing Logic.
J. Low Power Electron., 2012

Ultra Low Power Booth Multiplier Using Asynchronous Logic.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Static Average Case Power Estimation Technique for Block Ciphers.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Reversible online BIST using bidirectional BILBO.
Proceedings of the 7th Conference on Computing Frontiers, 2010


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