Jianzhuang Lu

According to our database1, Jianzhuang Lu authored at least 17 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Load balancing-oriented fault-tolerant NoC design.
Proceedings of the IEEE International Test Conference in Asia, 2024

2022
Towards Convolutional Neural Network Acceleration and Compression Based on Simonk-Means.
Sensors, 2022

TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip.
Sensors, 2022

Convolutional Neural Network Accelerator for Compression Based on Simon k-means.
Proceedings of the International Joint Conference on Neural Networks, 2022

HCER: A High Cost-Effectiveness Multi-Bit Fault-Tolerant NoC Router.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

2021
Vectorized Winograd's algorithm for Convolution Neural networks.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

Accelerating Depthwise Separable Convolutions with Vector Processor.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

2020
An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs.
Sensors, 2020

Dynamic GMMU Bypass for Address Translation in Multi-GPU Systems.
Proceedings of the Network and Parallel Computing, 2020

A Research and Design of Lightweight Convolutional Neural Networks Accelerator Based on Systolic Array Structure.
Proceedings of the ICRAI 2020: 6th International Conference on Robotics and Artificial Intelligence, 2020

A Design of GEMM Parallel Computing Accelerator Based on Vector SIMD Technology.
Proceedings of the ICCTA 2020: 6th International Conference on Computer and Technology Applications, 2020

2015
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2011
Design and chip implementation of a heterogeneous multi-core DSP.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP.
J. Comput. Sci. Technol., 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2004
A Case of SCMP with TLS.
Proceedings of the Parallel and Distributed Processing and Applications, 2004

2003
Predicate Analysis Based on Path Information.
Proceedings of the Advanced Parallel Programming Technologies, 5th International Workshop, 2003


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