Jianye Wang

Orcid: 0000-0003-4664-1201

According to our database1, Jianye Wang authored at least 21 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A subset simulation analysis framework for rapid reliability evaluation of series-parallel cold standby systems.
Reliab. Eng. Syst. Saf., January, 2024

Miniaturized bandpass filter with ultrawide-stopband and high selectivity using glass-based IPD technology.
Microelectron. J., 2024

Occlusion-Aware 3D Motion Interpretation for Abnormal Behavior Detection.
CoRR, 2024

ASL champ!: a virtual reality game with deep-learning driven sign recognition.
Comput. Educ. X Real., 2024

2023
Multivariate Time-Series Prediction in Industrial Processes via a Deep Hybrid Network Under Data Uncertainty.
IEEE Trans. Ind. Informatics, 2023

Converged communication method of multi-source data about underground equipment based on internet of things.
Int. J. Inf. Commun. Technol., 2023

Research on wireless sensor privacy data measurement and classification model based on IoT technology.
Int. J. Inf. Commun. Technol., 2023

2022
MVFStain: Multiple virtual functional stain histopathology images generation based on specific domain mapping.
Medical Image Anal., 2022

Adaptive residual CNN-based fault detection and diagnosis system of small modular reactors.
Appl. Soft Comput., 2022

2021
An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

Comprehensive Analysis Identifying Wnt Ligands Gene Family for Biochemical Recurrence in Prostate Adenocarcinoma and Construction of a Nomogram.
J. Comput. Biol., 2020

2019
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A Research Based on Log Current Spectrum for Experiment Approaches to Diagnosis of Motor Broken Rotor Bar Fault.
Proceedings of the 12th International Congress on Image and Signal Processing, 2019

2018
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.
Microelectron. J., 2018

2017
Matrix completion-based MIMO radar imaging with sparse planar array.
Signal Process., 2017

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
The simplest nonconforming mixed finite element method for linear elasticity in the symmetric formulation on n-rectangular grids.
Comput. Math. Appl., 2016

Microsecond-Level Temperature Variation of Logic Circuits and Influences of Infrared Cameras' Parameters on Hardware Trojans Detection.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

2015
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015


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