Jianwei Jiang

According to our database, Jianwei Jiang authored at least 8 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design.

Zhongyang Liu, Haineng Zhang, Jianwei Jiang, Yanjie Jia, Yuqiao Xie, Shichang Zou, Zhengxuan Zhang

IEEE Trans. Very Large Scale Integr. Syst., 2022

2020

A Wide-Range-Supply-Voltage Sense Amplifier Circuit for Embedded Flash Memory.

Wenyi Zhu, Jianwei Jiang, Haineng Zhang, Yiran Xu, Jun Xiao, Guangjun Yang, Shichang Zou

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications.

Jianwei Jiang, Yiran Xu, Wenyi Zhu, Jun Xiao, Shichang Zou

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A charge pump system with new regulation and clocking scheme.

Wenyi Zhu, Jianwei Jiang, Dianpeng Lin, Jun Xiao, Guangjun Yang, Xiaoyun Li, Shichang Zou

IEICE Electron. Express, 2019

Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design.

Jianwei Jiang, Dianpeng Lin, Jun Xiao, Shichang Zou

Proceedings of the International Conference on IC Design and Technology, 2019

2018

A novel highly reliable and low-power radiation hardened SRAM bit-cell design.

Dianpeng Lin, Yiran Xu, Xiaonian Liu, Wenyi Zhu, Lihua Dai, Mengying Zhang, Xiaoyun Li, Xin Xie, Jianwei Jiang, Huilong Zhu, Zhengxuan Zhang, Shichang Zou

IEICE Electron. Express, 2018

A novel self-recoverable and triple nodes upset resilience DICE latch.

Dianpeng Lin, Yiran Xu, Xiaoyun Li, Xin Xie, Jianwei Jiang, Jiangchuan Ren, Huilong Zhu, Zhengxuan Zhang, Shichang Zou

IEICE Electron. Express, 2018

A novel SEU tolerant memory cell for space applications.

Dianpeng Lin, Yiran Xu, Xiaoyun Li, Xin Xie, Jianwei Jiang, Jiangchuan Ren, Huilong Zhu, Zhengxuan Zhang, Shichang Zou

IEICE Electron. Express, 2018