Jianshi Tang
Orcid: 0000-0001-8369-0067
According to our database1,
Jianshi Tang
authored at least 33 papers
between 2019 and 2024.
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Bibliography
2024
A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
HXNOR-PBNN: A Scalable and Parallel Spintronics Synaptic Architecture for Probabilistic Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Statistical Modeling of Time-Dependent Post-Programming Conductance Drift in Analog RRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the IEEE International Memory Workshop, 2024
2023
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci., December, 2023
Ultralow-Power Compact Artificial Synapse Based on a Ferroelectric Fin Field-Effect Transistor for Spatiotemporal Information Processing.
Adv. Intell. Syst., November, 2023
Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips.
Sci. China Inf. Sci., October, 2023
A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Uncertainty quantification via a memristor Bayesian deep neural network for risk-sensitive reinforcement learning.
Nat. Mac. Intell., July, 2023
BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
An RRAM retention prediction framework using a convolutional neural network based on relaxation behavior.
Neuromorph. Comput. Eng., March, 2023
Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Reliability of Memristive Devices for High-Performance Neuromorphic Computing: (Invited Paper).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
2022
Adaptive optimal output regulation for wheel-legged robot Ollie: A data-driven approach.
Frontiers Neurorobotics, September, 2022
Generic Cryo-CMOS Device Modeling and EDACompatible Platform for Reliable Cryogenic IC Design.
CoRR, 2022
Large-Scale Integrated Flexible Tactile Sensor Array for Sensitive Smart Robotic Touch.
CoRR, 2022
A Physical Reservoir Computing Model Based on Volatile Memristor for Temporal Signal Processing.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proc. IEEE, 2021
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.
IEEE J. Solid State Circuits, 2021
Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips.
Sci. China Inf. Sci., 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Impact of Bottom Electrode Roughness on the Analog Switching Characteristics in Nanoscale RRAM Array.
Proceedings of the Device Research Conference, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A circuit-algorithm codesign method to reduce the accuracy drop of RRAM based computing-in-memory chip.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019