Jiann-Shiun Yuan
Orcid: 0000-0002-2548-8327Affiliations:
- University of Central Florida, Department of Electrical and Computer Engineering, Orlando, USA
According to our database1,
Jiann-Shiun Yuan
authored at least 66 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on cecs.ucf.edu
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on orcid.org
On csauthors.net:
Bibliography
2024
Algorithms, April, 2024
Patterns, January, 2024
Ideological orientation and extremism detection in online social networking sites: A systematic review.
Intell. Syst. Appl., 2024
2023
ProtEC: A Transformer Based Deep Learning System for Accurate Annotation of Enzyme Commission Numbers.
IEEE ACM Trans. Comput. Biol. Bioinform., 2023
2022
AMPDeep: hemolytic activity prediction of antimicrobial peptides using transfer learning.
BMC Bioinform., December, 2022
J. Cheminformatics, 2022
Comput., 2022
2021
ACM J. Emerg. Technol. Comput. Syst., 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons.
Neurocomputing, 2020
Frontiers Artif. Intell., 2020
Developing a Robust Defensive System against Adversarial Examples Using Generative Adversarial Networks.
Big Data Cogn. Comput., 2020
Big Data Cogn. Comput., 2020
Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-Bridge.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
ESD Robustness of GaN-on-Si Power Devices under Substrate Biases by means of TLP/VFTLP Tests.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Utilizing Transfer Learning and Homomorphic Encryption in a Privacy Preserving and Secure Biometric Recognition System.
Comput., 2019
RazorNet: Adversarial Training and Noise Training on a Deep Neural Network Fooled by a Shallow Neural Network.
Big Data Cogn. Comput., 2019
Low-Side GaN Power Device Dynamic Ron Characteristics Under Different Substrate Biases.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Analysis and Simulation of Capacitor-Less ReRAM-Based Stochastic Neurons for the in-Memory Spiking Neural Network.
IEEE Trans. Biomed. Circuits Syst., 2018
Leveraging Image Representation of Network Traffic Data and Transfer Learning in Botnet Detection.
Big Data Cogn. Comput., 2018
An Experimental Evaluation of Fault Diagnosis from Imbalanced and Incomplete Data for Smart Semiconductor Manufacturing.
Big Data Cogn. Comput., 2018
Anomaly Generation Using Generative Adversarial Networks in Host-Based Intrusion Detection.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
ECG Arrhythmia Classification Using Transfer Learning from 2- Dimensional Deep CNN Features.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Emerg. Top. Comput., 2017
A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs.
J. Low Power Electron., 2017
CoRR, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Ultra-Low Power Successive Approximation Analog-to-Digital Converter Using Emerging Tunnel Field Effect Transistor Technology.
J. Low Power Electron., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Microelectron. Reliab., 2015
2014
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Microelectron. Reliab., 2013
2012
Microelectron. Reliab., 2012
Examination of hot carrier effects of the AlGaAs/InGaAs pHEMT through device simulation.
Microelectron. Reliab., 2012
2011
Microelectron. Reliab., 2011
Evaluation of gate oxide breakdown effect on cascode class E power amplifier performance.
Microelectron. Reliab., 2011
2010
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances.
Microelectron. Reliab., 2010
Voltage stress effect on class AB power amplifier and mixed-signal sample-hold circuit.
Microelectron. Reliab., 2010
Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance.
Microelectron. Reliab., 2010
2008
Microelectron. Reliab., 2008
Microelectron. Reliab., 2008
2006
Study of performance degradations in DC-DC converter due to hot carrier stress by simulation.
Microelectron. Reliab., 2006
J. Low Power Electron., 2006
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integr., 2006
2005
IEEE Trans. Educ., 2005
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers.
Proceedings of the 2005 International Conference on Computer Design, 2005
2004
2003
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
2002
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.
J. Syst. Archit., 2002
2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
1991
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991
Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991