Jianming Lei

According to our database1, Jianming Lei authored at least 11 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
A Fractional-<i>N C</i>P-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.
Microelectron. J., February, 2023

A DTC-based Fractional-<i>N</i> DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications.
Microelectron. J., 2023

2022
Efficient hardware design of a deep U-net model for pixel-level ECG classification in healthcare device.
Microelectron. J., 2022

A High Throughput and Configurable Pseudo-random Number Extension Generator for Lattice-based Post-quantum Cryptography.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2019
A 68-nW novel CMOS sub-bandgap voltage reference circuit.
Microelectron. J., 2019

2013
A CMOS low-noise amplifier for BCC applications.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011
An area-efficient 5GHz/10GHz dual-mode VCO with coupled helical inductors in 0.13-UM CMOS technology.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2008
A novel schmitt trigger with low temperature coeficient.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Clock control strategy of four-phase Dickson charge pump for power efficiency improvement.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A 90nm CMOS wide-band voltage-controlled ring oscillator for digital TV-tuner.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Dynamically Reconfigurable Cache for Low-Power Embedded System.
Proceedings of the Third International Conference on Natural Computation, 2007


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